09 Logic data


Logic data

Below you find a small example tracing logic data (verilog,..). A logic bit is made up by one of the following states:

  • #define FLX_STATE_0_BITS  0
  • #define FLX_STATE_1_BITS  1
  • #define FLX_STATE_Z_BITS  2
  • #define FLX_STATE_X_BITS  3
  • #define FLX_STATE_L_BITS  4
  • #define FLX_STATE_H_BITS  5
  • #define FLX_STATE_U_BITS  6
  • #define FLX_STATE_W_BITS  7
  • #define FLX_STATE_D_BITS  8
  • #define FLX_STATE_J_BITS  9

If you add a signal with type FLX_TYPE_LOGIC you will get a 1 bit logic. To add ad logic vector (e.g. a bus), add a descriptor with a bits declaration (e.g. default<bits=16>).
 

	// logic signals
	flxAddScope(trace, 1, 0, "Logics", "yep");
	flxAddSignal(trace, 2, 1, "bit", "desc", FLX_TYPE_LOGIC, 0);
	flxAddSignal(trace, 3, 1, "vector", "desc", FLX_TYPE_LOGIC, "default<bits=16>");
	flxAddScatteredSignal(trace, 4, 1, "scattered", 0, FLX_TYPE_LOGIC, 0, 0, 1);
	flxAddScatteredSignal(trace, 5, 1, "scattered", 0, FLX_TYPE_LOGIC, 0, 2, 5);
    

Logic data can be either passed as text or array of states (bytes).

// iterate over n

	// logic data using text
	flxWriteLogicTextAt(trace, 2, 0, n * 10 , 0, FLX_STATE_0_BITS, n&1?"1":"0", 1);
	flxWriteLogicTextAt(trace, 3, 0, 0, 1, FLX_STATE_0_BITS, n&1?"0011x1":"111uuu", 6);
	flxWriteLogicTextAt(trace, 4, 0, 0, 1, FLX_STATE_0_BITS, n&1?"uu":"0u", 2);
	flxWriteLogicTextAt(trace, 5, 0, 0, 1, FLX_STATE_0_BITS, n&1?"11x1":"1100", 4);

	// logic data using state arrays
	flxbyte states[4] = {FLX_STATE_1_BITS,FLX_STATE_1_BITS,FLX_STATE_X_BITS,FLX_STATE_X_BITS};
	flxWriteLogicStatesAt(trace, 3, 0, 5 , 1, FLX_STATE_U_BITS, states, 4);

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